In one conventional integrated circuit test technique, the integrated circuit includes built-in scan chains for testing. During testing of the integrated circuit, each scan chain receives, via a respective input terminal of the integrated circuit, test inputs from an external test input generator, and generates test outputs in response to these inputs. The test outputs generated by the scan chains are supplied, via respective output terminals of the integrated circuit, to an external test analyzer. The test analyzer compares the test outputs that it receives to expected outputs to determine therefrom whether the integrated circuit is operating properly.
The cost of testing integrated circuits using this conventional technique typically is related to factors such as the time involved in carrying out the test and test complexity. Typically, these factors may be related to other factors, such as, the volume of test inputs supplied to the integrated circuit by the test input generator, the volume of test outputs analyzed by the test analyzer, and the cost of the test input generator and the test analyzer. By increasing the number of input and output terminals via which such inputs and outputs are propagated to and from, respectively, the integrated circuit, the time involved in carrying out such testing may be reduced, at least to some extent. However, increasing the number of input and output terminals may result in increasing the integrated circuit's packaging size and manufacturing cost.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.